Thin-film transistors have been commonly used in static random access memory devices (SRAM) and active matrix liquid crystal displays (AMLCD). Methods of fabricating thin-film transistors have been actively researched. Using self-alignment technique in fabricating thin-film transistors is desirable because it ensures that the channel gap between the source and the drain electrodes is optimized and is substantially uniform. Hayden et al. disclosed a self-aligned thin-film transistor in U.S. Pat. No. 5,235,189 issued on Aug. 10, 1993. Possin et al. disclosed a self-aligned thin-film transistor having reduced end leakage in U.S. Pat. No. 5,241,192, issued on Aug. 31, 1993 and its fabrication method in U.S. Pat. No. 5,324,674, issued on Jun. 28, 1994. A method of fabricating a self-aligned thin-film transistor with a lift-off technique was disclosed by Kwasnick et al. in U.S. Pat. No. 5,391,507, issued on Feb. 21, 1995. Rha presented a different thin-film transistor having self-aligned diffused source and drain regions to improve the ratio of on to off current and the method of fabricating such a transistor in U.S. Pat. No. 5,403,761, issued on Apr. 4, 1995.
Various ongoing developments have been dedicated to improving the switching speed, decreasing the loading current or to increase the dynamic range of thin-film transistors. As an example, Zhao et al. presented a technique of fabricating vertical submicron polysilicon thin-film transistors without using submicron lithographic equipment in a paper entitled "A Vertical Submicron Polysilicon Thin-Film Transistor Using A Low Temperature Process" in IEEE Electron Device Letters, vol. 15, No. 10, Oct. 1994.
A lightly doped drain can reduce the electric field in the area near the drain of a thin-film transistor device. Consequently, the loading current of the device can be decreased. A method of fabricating thin-film transistors having lightly doped drains was disclosed by Manning et al. in U.S. Pat. No. 5,334,862, issued on Aug. 2, 1994. A thin-film transistor having an asymmetrical lightly doped drain structure was further disclosed by Chae in U.S. Pat. No. 5,442,215, issued on Aug. 15, 1995. Process including lightly doped drain technique has been commonly used in the thin-film transistors of a CMOS device manufacturing process with silicon wafer substrate. Such a thin-film transistor is usually top-gated which has a source, a drain and a channel region that are formed underlying a gate region. The structure is co-planar. In AMLCD, however, an inverted staggered structure that has a source, a drain and a channel region formed overlying a gate region is often adopted for the thin-film transistor that has a glass substrate. When a polysilicon thin-film transistor having lightly doped drain is manufactured for the inverted staggered structure, the off-current of the transistor is normally too large.